No, its no. The ARM instruction set may be more limited compared to the x86 instruction set but this has nothing to do with the architecture of the processors. The ARM instruction set is not a subset of x86 instructions. They are encoded differently and the processor executes them in a different way. The registers … Read more
You seem not to have understood how the CPU and the bus are working: As you knows network i/o is based on nic interrupt. An interrupt is a mechanism which is starting a short program whenever the hardware (for example the network card) requests the CPU to do so. An interrupt only starts this short … Read more
MUL BX OR AX, DX On older machines this might not be very fast compared to longer answers. 10 solved Compact implementation of logical AND in x86 assembly [closed]
It looks like you are trying to do something similar to this: #include <stdio.h> double hullSpeed(double lgth) { double result; __asm__( “fldl %1\n\t” //st(0)=>st(1), st(0)=lgth . FLDL means load double float “fsqrt\n\t” //st(0) = square root st(0) “fmulp\n\t” //Multiplies st(0) and st(1) (1.34). Result in st(0) : “=&t” (result) : “m” (lgth), “0” (1.34)); return … Read more
Is it possibile, given a sequence of bytes x86 instructions into a stream of random bytes, to decode their instructions? Yes. Many kinds of processors do it. It is one of the easiest task they have. Are opcodes of a fixed length No. or is there any way to detect those instructions? The first byte(s) … Read more
First of all, the TSS is a historical wart. Once in a time (a.k.a: early 1980’s), people at Intel tought that hardware context-switching, instead of software context-switching, was a great idea. They were greatly wrong. Hardware context-switching has several noticeable disadvantages, and, as it was never implemented appropiately, had miserable performance. No sane OS even … Read more
1) Yes 2) Yes 3) No (As said above without running a virtual machine or emulating or something) 4) Yes http://www.techsupportalert.com/content/32-bit-and-64-bit-explained.htm There is some reading for you to help with why 🙂 0 solved Application 32/64 bit and OS 32/64 bit [closed]
This an ancient DOS Protected Mode Interface system call to set a protected mode interrupt vector. See eg http://www.delorie.com/djgpp/doc/dpmi/api/310205.html. The compiler was probably DJGPP. Porting this to a different OS and/or runtime system will require a redesign from scratch to reimplement whatever functionality the interrupt handlers provided under DPMI. Good luck to you with that. … Read more
Jester’s suggestion to write it in C is probably a good one, esp. if it can be inlined into calls where some of the args are compile-time constants. Your example use-case passes mostly compile-time-constant args, including the function pointer. Any decent optimizing compiler will inline this and optimize away the indirection into just a normal … Read more
A loop is implemented like this: loop down: mov ecx, 10 ; count from 10 to 0 label: dec ecx loop label loop up: xor ecx,ecx ; count from 0 to 10 label: inc ecx cmp ecx, 10 jne label Now think how your algorithm works and how to apply this information. 4 solved Division … Read more
(My assembly is a bit rusty, anyone please correct me if I’m wrong): esp is the current stack-pointer, which is where locals and parameters typically live. esp+8 would access an item that is 8 bytes offset from the current stack-frame address. The [x] denotes a dereferencing, so the local is a pointer type. This value … Read more
In x86 you don’t need a cascading sequence of jumps, since jmp can jump over the whole segment. Just a conditional jump like jne has a limited range. So you can change an errorneous conditional jump to a combination of an unconditional near jump and a conditional short jump: As an example, change .MODEL small … Read more