[Solved] What is the meaning or difference between Simulation and Synthesis in VHDL? [closed]
As you’ve probably realized by now, VHDL is not a programming language but a Hardware Description Language. It is very easy to get confused about the terminology cause HDL doesn’t work like software. Simulation consists of using a simulator (surprise) such as ModelSim to interpret your VHDL code while stimulating inputs to see what the … Read more