[Solved] some arm inline assembly [closed]

Question

As mentioned by the commenters LDR r3,#0xaabbccdd is not a valid instruction. Immediates in ARM opcodes are on the form ZeroExtend(imm8) ROR (imm4*2), which would allow you to represent e.g. 0xaa000000, 0x00bb0000 and even 0xd000000d – but not e.g. 0xaabb0000 or 0xaabbccdd.

Assemblers typically provide a pseudo-instruction for loading 32-bit immediates, e.g. in GAS you can do:

ldr r3,=0xaabbccdd

Which would be encoded as a PC-relative load – i.e. ldr r3,[pc,#offset]. The offset (and therefore the exact instruction encoding) depends on the distance from the instruction to the literal pool where the value is stored.

Accepted Answer

As mentioned by the commenters LDR r3,#0xaabbccdd is not a valid instruction. Immediates in ARM opcodes are on the form ZeroExtend(imm8) ROR (imm4*2), which would allow you to represent e.g. 0xaa000000, 0x00bb0000 and even 0xd000000d – but not e.g. 0xaabb0000 or 0xaabbccdd.

Assemblers typically provide a pseudo-instruction for loading 32-bit immediates, e.g. in GAS you can do:

ldr r3,=0xaabbccdd

Which would be encoded as a PC-relative load – i.e. ldr r3,[pc,#offset]. The offset (and therefore the exact instruction encoding) depends on the distance from the instruction to the literal pool where the value is stored.