As you’ve probably realized by now, VHDL is not a programming language but a Hardware Description Language. It is very easy to get confused about the terminology cause HDL doesn’t work like software.
Simulation consists of using a simulator (surprise) such as ModelSim to interpret your VHDL code while stimulating inputs to see what the outputs would look like. The results are typically displayed in a waveform chart, so whenever you see a waveform chart odds are it’s about simulation. Simulation takes place in a computer never involving an actual FPGA. Simulation software can be very expensive, I recently came across a free online tool with fair simulation capabilities: EDA Playground
Synthesizing is a completely different thing. Once your design has been proved to work in simulation, the VHDL code goes through a tough process that figures how to implement, simplify, layout and route the actual resources in the FPGA to perform the functions it’s supposed to (think of it as the hardware equivalent to compiling). The output of this process is a file that is downloaded to the FPGA.
Hope it helps!
solved What is the meaning or difference between Simulation and Synthesis in VHDL? [closed]