system-verilog

module TB; reg ***[2:0]*** a, b, c; initial begin a = 3; b = 4; $display (“a = %d, b = %d, c=%d\n”, a, b, c); c <= a + b; $display (“a = %d, b = %d, c=%d\n”, a, b, c); a <= 10; b <= 2; c = a + b; $display (“a … Read more