[Solved] In Makefiles GCC C programs, What are .d files and also what is a wildcard.? [closed]

Question

These *.d files usually (and just conventionally) are make dependencies (but perhaps, and unlikely, D-language source code).

The GCC compiler knows about -M (and related) preprocessor option, which asks make to ….

Instead of outputting the result of preprocessing, output a rule suitable for make describing the dependencies of the main source file.

With the help of a few good Makefile tricks, you could write a Makefile automatically dealing with dependencies, e.g. with things like

 ## dependencies of foo.c
 foo.d: foo.c
      $(COMPILE.c) -M $^ -o $@
 ## include them
 -include foo.d

About $(wildcard *.c), read the GNU make documentation, section on file name functions. So $(wildcard *.c) is globbing the *.c by make expanding it into the list of files ending with .c; you could use it e.g. to define a make variable: SOURCE_FILES= $(wildcard *.c), etc.

See also this, that and that examples.

Don’t forget to try make -p to understand all the good builtin rules known by GNU make…. Use make --trace or remake-x for debugging your Makefile-s.

Accepted Answer

These *.d files usually (and just conventionally) are make dependencies (but perhaps, and unlikely, D-language source code).

The GCC compiler knows about -M (and related) preprocessor option, which asks make to ….

Instead of outputting the result of preprocessing, output a rule suitable for make describing the dependencies of the main source file.

With the help of a few good Makefile tricks, you could write a Makefile automatically dealing with dependencies, e.g. with things like

 ## dependencies of foo.c
 foo.d: foo.c
      $(COMPILE.c) -M $^ -o $@
 ## include them
 -include foo.d

About $(wildcard *.c), read the GNU make documentation, section on file name functions. So $(wildcard *.c) is globbing the *.c by make expanding it into the list of files ending with .c; you could use it e.g. to define a make variable: SOURCE_FILES= $(wildcard *.c), etc.