[Solved] Implementing Sequential Circuit in Verilog

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seq_circuit1

  • You can’t instantiate submodules (your FFs) inside an always block.
    Move them outside, either before or after.
  • Your instantiations for jkfflop are missing the clk input signal.
  • based on your diagram, your inputs to the FFs should be combinational logic, not sequential, and should therefore use an always @(*) block, not a clocked one.

jkfflop

  • if statements in verilog are only valid inside a generate, always or inital block. Since this is a FF, you’ll want an always @(posedge clk) or always @(negedge clk)
  • If using an always block, replace the assign statements with non-blocking assignments (<=). We use NBA’s here instead of a blocking assignments (=), as it’s an edge-triggered block.
  • If assigning a value to Q inside an always block, change output Q to output reg Q

solved Implementing Sequential Circuit in Verilog