[Solved] 1 bit stream in verilog [closed]

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To convert Serial to Parallel, you need some way to identify the end or start of sequence. Something like the following should get you off to a start:

input            clk;
input            end_of_sequence;
input            sdata;
output reg [9:0] result;
//10 bit transmission

reg [9:0] pdata;

always @(posedge clk) begin
  // Shift serial data in
  pdata <= {pdata[8:0, sdata};
end

always @(posedge clk) begin
  if (end_of_sequence ) begin
    // at end of shifted data store the full parallel word
    result <= pdata;
  end
end

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solved 1 bit stream in verilog [closed]